In various treatment processes of a semiconductor wafer, a so-called pre-alignment in which the semiconductor wafer is aligned in a certain direction is performed. In the pre-alignment of the semiconductor wafer, an orientation flat formed at the outer circumference of the semiconductor wafer is used. However, some semiconductor wafers have a plurality of orientation flats.
For example, Japanese Laid-Open Patent Publication No. HEI 02-130850 discloses a technology of providing an additional orientation flat (sub orientation flat) as well as a primary orientation flat (main orientation flat) and thereby using the sub orientation flat as a marker for distinguishing between front and rear surfaces of a semiconductor wafer. In this technology, before a semiconductor wafer is cut off from an ingot, a spiral sub-notch, aside from a main notch for an orientation flat, is provided on the outer circumferential surface of the ingot. Thus, according to the distance from a main orientation flat to a sub orientation flat formed by cutting a semiconductor wafer, the cut-off order from a seed side is identified, thereby distinguishing the front and rear surfaces of the semiconductor wafer. In this technology, it is possible to clearly distinguish the main orientation flat from the sub orientation flat according to their sizes.
Also, the Japanese Laid-Open Patent Publication No. 2004-356411 discloses a technology of distinguishing between front and rear surfaces of a semiconductor wafer by using a main orientation flat and two sub orientation flats. In this technology, a main orientation flat is imaged by two imaging means, and one sub orientation flat or a circular arc portion opposite to the sub orientation flat is imaged by one imaging means, while the front and rear surfaces of the semiconductor wafer are distinguished from each other according to whether the portion imaged by the latter imaging means is straight line or curved line. In this technology, it is possible to distinguish a main orientation flat from a plurality of sub orientation flats according to their sizes.
The technologies disclosed in the patent publications mentioned above are related to the distinguishment between front and rear surfaces of a semiconductor wafer using a main orientation flat and a sub orientation flat. Accordingly, they are based on the assumption that a main orientation flat is used for a pre-alignment. However, in the case where there are a plurality of orientation flats with the same size, it may be impossible to appoint any one of the orientation flats as an orientation flat for pre-alignment due to the same size of the orientation flats.
Hereinafter, a pre-alignment method which has been used for a semiconductor wafer having a plurality of orientation flats will be briefly described with reference to FIGS. 7a, 7b and 8. For example, as shown in FIG. 7a, when a semiconductor wafer W formed with three orientation flats is subjected to a pre-alignment process, semiconductor wafer W is disposed on a rotating body R for the pre-alignment, and is rotated by rotating body R. Herein, an orientation flat of semiconductor wafer W is detected by using an optical sensor having a light emitting element and a light receiving element, disposed in the neighborhood of rotating body R. When a light beam from the light emitting element passes through the outside of an orientation flat of rotating semiconductor wafer W, the light quantity of the light beam which passed through the outside is detected by the light receiving element. Herein, a control device determines the size of the orientation flat based on a detection signal of the light receiving element. As the light quantity detected by the light receiving element increases, the size of the orientation flat increases. These two values are in proportion to each other. FIG. 7b shows a graph illustrating the relationship between the detection position of the orientation flat and the light quantity detected by the light receiving element. In this graph, the horizontal axis denotes a coordinate position along the entire circumference of semiconductor wafer W, and the ordinate axis denotes a light quantity detected by the light receiving element. The peak area of the graph denotes the light quantity of a light beam which passed through the outside of the orientation flat of semiconductor wafer W, and corresponds to the area of a notch portion formed by the orientation flat. In a conventional pre-alignment, the largest orientation flat is used as a reference orientation flat for the pre-alignment.
Hereinafter, a conventional pre-alignment method will be described with reference to the flow chart illustrated in FIG. 8. First, the outer circumference of semiconductor wafer W is detected by the optical sensor to obtain data on the outer circumference of semiconductor wafer W (step S101). Then, eccentric components (an eccentric angle and an eccentricity amount) are calculated from the center of rotating body R with respect to the center of semiconductor wafer W based on the outer circumference data of semiconductor wafer W (step S102). Next, it is determined if the eccentricity amount is large (step S103). If the eccentricity amount is large, the eccentricity amount is corrected (step S104), and then the process proceeds back to step S101 to repeat the above described operations. When the eccentricity amount is corrected, it is determined that the center of semiconductor wafer W corresponds to the center of rotating body R in step S103, and then the number of orientation flats is detected by using the optical sensor (step S105). Also, as a method for calculating the eccentric components in step S102, Japanese Patent No. 2796296 discloses a method for employing a wafer in a pre-alignment method.
Then, based on the result detected by the optical sensor, it is determined if the number of the orientation flats is zero (step S106). If the number is determined not to be zero, the positions of the orientation flats are identified with reference to the data on the graph illustrated in FIG. 7b (step S107), and then the lengths of the respective orientation flats are calculated (step S108). Next, it is determined if an appointed flat No. is higher than the number of the orientation flats (step S109). If the appointed flat No. is not higher than the number of the orientation flats, the longest orientation flat is set as a reference orientation flat (step S110). After the setting of the reference orientation flat, orientation flats corresponding to the appointed flat No. with respect to the reference orientation flat are detected (step S111), the angle of rotating body R is set according to positions of the detected orientation flats (step S112), and the pre-alignment is finished. If the number of the orientation flats is zero in step S106, or if the appointed flat No. is higher than the number of the orientation flats in step S109, the process is determined to be in error, thereby stopping the alignment. Herein, the appointed flat No. denotes a parameter indicating a clockwise nth orientation flat from a reference orientation flat (or a reference circular arc) i.e., the first orientation flat. The angle should be adjusted to the nth orientation flat.
However, in a method for appointing a reference orientation flat based on the lengths of orientation flats, if there are a plurality of orientation flats with the same length, it was impossible to appoint the reference orientation flat for a pre-alignment on semiconductor wafer W due to the same length of the orientation flats.